Field of the Invention
The invention relates to an input circuit for an integrated circuit.
Input circuits of integrated circuits for digital signals, which have two levels that are close to two supply potentials of the input circuit, are often produced using an inverter. Such input signals (hereafter "standard digital signals") are encountered, for example, in so-called TTL logic or LVTTL logic (low voltage TTL).
On the other hand, other integrated circuits are supplied with input signals that have two levels that respectively represent a positive and negative difference in relation to a reference level. For such input signals (hereafter "differential signals") it is possible to use, as input circuits, differential amplifiers to which the reference level is fed as a comparative value, while the input signal is applied to their input. Such differential signals are used, for example, in so-called SSTL logic. Values typical of SSTL logic are 1.4 V for the reference level, 1.44 V-0.3 V for the negative level and 1.4 V+0.3 V for the positive level.
U.S. Pat. No. 5,455,524 describes an input circuit that has a series circuit containing two inverters and a series circuit containing two differential amplifiers. In a first operating mode, the two differential amplifiers are activated and the inverters are deactivated, and ECL input signals are fed to the circuit. In a second operating mode, the differential amplifiers are deactivated and the inverters are activated, and CMOS input signals are fed to the circuit. The differential amplifiers and inverters are respectively embodied by different components.